/* 8n1 UART module - transmit only
   License: GPLv3
*/
module uart_tx_8n1(input clk, input[7:0] txbyte, input senddata, output txcomplete, output tx);
	/* Parameters */
	parameter STATE_IDLE = 8'd0;
	parameter STATE_STARTTX = 8'd1;
	parameter STATE_TXING = 8'd2;
	parameter STATE_TXDONE = 8'd3;

	/* State variables */
	reg [7:0] state = 8'b0;
	reg [7:0] buf_tx = 8'b0;
	reg [7:0] bits_sent = 8'b0;
	reg txbit = 1'b1;
	reg txdone = 1'b0;

	/* Wiring */
	assign tx = txbit;
	assign txcomplete = txdone;

	/* Transmit on clock */
	always @ (posedge clk) begin
		/* Send data if instructed to (rather than idle) */
		if (senddata == 1 && state == STATE_IDLE) begin
			state <= STATE_STARTTX;
			buf_tx <= txbyte;
			txdone <= 1'b0;
		end
			else if (state == STATE_IDLE) begin
				/* If not instructed to send data, just idle */
				txbit <= 1'b1;
				txdone <= 1'b0;
			end

		/* Send start bit (low) */
		if (state == STATE_STARTTX) begin
			txbit <= 1'b0;
			state <= STATE_TXING;
		end

		if (state == STATE_TXING && bits_sent < 8'd8) begin
			txbit <= buf_tx[0];
			buf_tx <= buf_tx >> 1;
			bits_sent <= bits_sent + 1;
		end
			else if (state == STATE_TXING) begin
				/* Send stop bit (high) */
				txbit <= 1'b1;
				bits_sent <= 8'b0;
				state <= STATE_TXDONE;
			end

		/* TX done */
		if (state == STATE_TXDONE) begin
			txdone <= 1'b1;
			state <= STATE_IDLE;
		end
	end

endmodule