/*
 * Top module for iCEstick UART
 * Blinks all LEDs and transmits a holy message over UART.
 * Licence: GPLv3
 */

module top(input hwclk, output LED1, output LED2, output LED3, output LED4, output LED5, output ftdi_tx, input ftdi_rx);
	/* ~9600Hz clock (12MHz source clock) */
	reg clk_9600 = 1'b0;
	reg [9:0] cntr_9600 = 10'b0;
	parameter period_9600 = 625;

	/* ~19200Hz clock (12MHz source clock) */
	reg clk_19200 = 1'b0;
	reg [8:0] cntr_19200 = 9'b0;
	/* Should be 312.5, but 313 is as close as we can get */
	parameter period_19200 = 313;

	/* ~4800Hz clock (12MHz source clock) */
	reg clk_4800 = 1'b0;
	reg [10:0] cntr_4800 = 11'b0;
	parameter period_4800 = 1250;

	/* Buffer for FIFO */
	reg [31:0] buff = 32'd0;
	reg count = 3'b0;
	/* Byte buffer to send over UART */
	reg [7:0] uart_txbyte;
	/* Idle at first */
	reg uart_send = 1'b0;
	/* Set to 1 after byte transmission is complete */
	wire uart_txed;

	/* Byte to recv to */
	wire [7:0] uart_rxbyte;
	/* Recv data rather than idle */
	reg uart_recv = 1'b1;
	/* Set to 1 after byte retrival is complete */
	wire uart_rxed;

	/* UART transmitter module - 8 bits, no parity, 1 stop bit
				9600 baud	byte to be transmitted	send on baud clock	input: tx completed	output: UART tx pin */
	uart_tx_8n1 transmitter(.clk(clk_9600), .txbyte(uart_txbyte), .senddata(uart_send), .txcompleted(uart_txed), .tx(ftdi_tx));
	/* UART reciever module - 8 bits, no parity, 1 stop bit
				9600 baud	byte to recieve to	recv on baud clock	input: rx completed	output: UART rx pin */
	uart_rx_8n1 reciever(.clk(clk_9600), .rxbyte(uart_rxbyte), .recvdata(uart_recv), .rxcompleted(uart_rxed), .rx(ftdi_rx));

	/* LED register */
	reg ledval = 1'b0;
	/* Assign ledval to all LEDs */
	assign LED1 = ledval;
	assign LED2 = ledval;
	assign LED3 = ledval;
	assign LED4 = ledval;
	assign LED5 = ledval;

	/* Reduced clock generator */
	always @ (posedge hwclk) begin
		/* ~9600Hz clock */
		cntr_9600 <= cntr_9600 + 1;
		if (cntr_9600 == period_9600) begin
			clk_9600 <= ~clk_9600;
			cntr_9600 <= 10'b0;
		end

		/* ~19200Hz clock */
		cntr_19200 <= cntr_19200 + 1;
		if (cntr_19200 == period_19200) begin
			clk_19200 <= ~clk_19200;
			cntr_19200 <= 9'b0;
		end

		/* ~4800Hz clock */
		cntr_4800 <= cntr_4800 + 1;
		if (cntr_4800 == period_4800) begin
			clk_4800 <= ~clk_4800;
			cntr_4800 <= 11'b0;
		end
	end

	/* Blink leds if we just txed - 1/2 of clock rate of the main loop prevents LEDs from blinking too fast. */
	always @ (posedge clk_4800) begin
		if (uart_txed == 1) ledval <= ~ledval;
	end

	/* Read/write loop is clocked at ~2x the baud */
	always @ (posedge clk_19200) begin

		/* Get rx'ed byte and hand it over to tx and enable tx'ing */
		if (uart_rxed == 1) begin
			uart_recv <= 1'b0;
			uart_txbyte <= uart_rxbyte;
			uart_send <= 1'b1;
		end

		/* Stop sending after character has been sent */
		if (uart_txed == 1) begin
			uart_send <= 1'b0;
			uart_recv <= 1'b1;
		end

	end

endmodule