initial commit

1 files changed, 48 insertions, 0 deletions

diff --git a/top.v b/top.v
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+//License: GPLv3
+module top(input hwclk, output LED1, output LED2, output LED3, output LED4, output LED5, output ftdi_tx, input ftdi_rx);
+	/* ~4800Hz clock (12MHz source clock) */
+	reg clk_4800 = 1'b0;
+	reg [10:0] cntr_4800 = 11'b0;
+	parameter period_4800 = 1250;
+
+	/* LED 1-3 are disabled */
+	reg offleds = 1'b0;
+	assign LED1 = offleds;
+        assign LED2 = offleds;
+        assign LED3 = offleds;
+
+	/* LED 4-5 is for rx and tx */
+	reg ledrx = 1'b0;
+	reg ledtx = 1'b0;
+	assign LED4 = ledrx;
+	assign LED5 = ledtx;
+
+	/* assign ftdi_tx to a register as writing to a wire isn't permitted */
+	reg tx = 1'b0;
+	assign tx = ftdi_tx;
+
+	/* generate reduced clocks and also loopback uart at 12MHz */
+	always @ (posedge hwclk) begin
+		/* ~4800Hz clock */
+		cntr_4800 <= cntr_4800 + 1;
+		if (cntr_4800 == period_4800) begin
+			clk_4800 <= ~clk_4800;
+			cntr_4800 <= 11'b0;
+		end
+
+		/* loopback the UART signal directly from the FTDI RX to TX
+		* pin - the base clock is used, so the bitbanging software can
+		* decide what clockrate to use */
+		tx <= ftdi_rx;
+	end
+
+	/* Blink leds if we just txed - 1/2 of clock rate of the main loop prevents LEDs from blinking too fast. */
+	always @ (posedge clk_4800) begin
+		if (ftdi_rx == 0) ledrx <= ~ledrx;
+		if (ftdi_tx == 0) ledtx <= ~ledtx;
+	end
+
+endmodule
+
+
+