cleaned up sourceHEADmaster

1 files changed, 4 insertions, 24 deletions

diff --git a/top.v b/top.v
index d4da4e9..2ee3a71 100644
--- a/top.v
+++ b/top.v
@@ -86,39 +86,19 @@ module top(input hwclk, output LED1, output LED2, output LED3, output LED4, outp
 	/* Read/write loop is clocked at ~2x the baud */
 	always @ (posedge clk_19200) begin
 
-
-		if (uart_rxed == 1 && count < 4) begin
-			/* garbage */
-			buff[count*8+7:count*8] <= uart_rxbyte;
-			count <= count + 1;
-		end
-
-		if (count > 0 && uart_send == 0) begin
-			/* garbage */
-			uart_txbyte <= buff[7:0];
-			buff <= 8 >> buff;
-			count <= count - 1;
-			uart_send <= 1'b1;
-		end
-
-		/* Stop sending after character has been sent */
-		if (uart_txed == 1) uart_send <= 1'b0;
-
-
-/*		if (uart_rxed == 1) begin
+		/* Get rx'ed byte and hand it over to tx and enable tx'ing */
+		if (uart_rxed == 1) begin
 			uart_recv <= 1'b0;
 			uart_txbyte <= uart_rxbyte;
 			uart_send <= 1'b1;
 		end
-*/
+
 		/* Stop sending after character has been sent */
-/*		if (uart_txed == 1) begin
+		if (uart_txed == 1) begin
 			uart_send <= 1'b0;
 			uart_recv <= 1'b1;
 		end
 
-*/
-
 	end
 
 endmodule