initial commitHEADmaster

3 files changed, 103 insertions, 0 deletions

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..c739e6a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,34 @@
+PROJ = uart_passthrough
+DEVICE = hx1k
+PKG = tq144
+PCF = pins.pcf
+
+FILES = top.v
+
+.PHONY: all clean burn
+
+all: $(PROJ).bin
+
+%.json: $(FILES)
+	# Lint to catch mistakes
+	verilator --lint-only $(FILES)
+	# synthesize using Yosys
+	yosys -ql yosys.log -p "synth_ice40 -top top -json $(PROJ).json" $(FILES)
+
+%.asc: %.json
+	# Place and route using nextpnr
+	nextpnr-ice40 --$(DEVICE) --package $(PKG) --pcf $(PCF) --json $< --asc $@
+
+%.rpt: %.asc
+	# Timing
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%.bin: %.asc
+	# Convert to bitstream using IcePack
+	icepack $< $@
+
+burn:   $(PROJ).bin
+	iceprog $<
+
+clean:
+	rm -f *.json *.asc *.bin *.vcd *.log
diff --git a/pins.pcf b/pins.pcf
new file mode 100644
index 0000000..b93ec18
--- /dev/null
+++ b/pins.pcf
@@ -0,0 +1,12 @@
+set_io LED1 99
+set_io LED2 98
+set_io LED3 97
+set_io LED4 96
+set_io LED5 95
+set_io hwclk 21
+# FTDI pins for UART
+set_io ftdi_tx 8
+set_io ftdi_rx 9
+# pins on header
+set_io ext_tx 87
+set_io ext_rx 78
diff --git a/top.v b/top.v
new file mode 100644
index 0000000..3b91d55
--- /dev/null
+++ b/top.v
@@ -0,0 +1,57 @@
+//License: GPLv3
+module top(input hwclk, output LED1, output LED2, output LED3, output LED4, output LED5, output ftdi_tx, input ftdi_rx, output ext_tx, input ext_rx);
+	/* ~4800Hz clock (12MHz source clock) */
+	reg clk_4800 = 1'b0;
+	reg [10:0] cntr_4800 = 11'b0;
+	parameter period_4800 = 1250;
+
+	/* turn LED's 1-3 off */
+	reg offleds = 1'b0;
+	assign LED1 = offleds;
+	assign LED2 = offleds;
+	assign LED3 = offleds;
+
+	/* LED 4-5 is for rx and tx */
+	reg ledrx = 1'b0;
+	reg ledtx = 1'b0;
+	assign LED4 = ledrx;
+	assign LED5 = ledtx;
+
+	/* can't write directly to wires, so assign to registers */
+	reg tx = 1'b0;
+	assign tx = ext_tx;
+	reg rx = 1'b0;
+	assign rx = ftdi_tx;
+
+	/* generate reduced clocks and also loopback uart at 12MHz */
+	always @ (posedge hwclk) begin
+		/* ~4800Hz clock */
+		cntr_4800 <= cntr_4800 + 1;
+		if (cntr_4800 == period_4800) begin
+			clk_4800 <= ~clk_4800;
+			cntr_4800 <= 11'b0;
+		end
+
+		/* just tx and rx and the full 12MHz clock - let the
+		 * bitbanging software decide on the clock (just works for
+		 * unknown reasons) */	
+
+	       /* get a bit from ftdi_rx (i.e. input coming from the computer
+	        * and pass it to the external tx port */
+		tx <= ftdi_rx;
+
+		/* get a bit from the external rx port and pass it to ftdi_tx
+		 * (i.e. bit to the computer)*/
+		rx <= ext_rx;
+	end
+
+	/* blink leds if we just txed - 1/2 of clock rate of the main loop prevents LEDs from blinking too fast */
+	always @ (posedge clk_4800) begin
+		if (ftdi_rx == 0) ledrx <= ~ledrx;
+		if (ftdi_tx == 0) ledtx <= ~ledtx;
+	end
+
+endmodule
+
+
+