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//License: GPLv3
module top(input hwclk, output LED1, output LED2, output LED3, output LED4, output LED5, output ftdi_tx, input ftdi_rx, output ext_tx, input ext_rx);
/* ~4800Hz clock (12MHz source clock) */
reg clk_4800 = 1'b0;
reg [10:0] cntr_4800 = 11'b0;
parameter period_4800 = 1250;
/* turn LED's 1-3 off */
reg offleds = 1'b0;
assign LED1 = offleds;
assign LED2 = offleds;
assign LED3 = offleds;
/* LED 4-5 is for rx and tx */
reg ledrx = 1'b0;
reg ledtx = 1'b0;
assign LED4 = ledrx;
assign LED5 = ledtx;
/* can't write directly to wires, so assign to registers */
reg tx = 1'b0;
assign tx = ext_tx;
reg rx = 1'b0;
assign rx = ftdi_tx;
/* generate reduced clocks and also loopback uart at 12MHz */
always @ (posedge hwclk) begin
/* ~4800Hz clock */
cntr_4800 <= cntr_4800 + 1;
if (cntr_4800 == period_4800) begin
clk_4800 <= ~clk_4800;
cntr_4800 <= 11'b0;
end
/* just tx and rx and the full 12MHz clock - let the
* bitbanging software decide on the clock (just works for
* unknown reasons) */
/* get a bit from ftdi_rx (i.e. input coming from the computer
* and pass it to the external tx port */
tx <= ftdi_rx;
/* get a bit from the external rx port and pass it to ftdi_tx
* (i.e. bit to the computer)*/
rx <= ext_rx;
end
/* blink leds if we just txed - 1/2 of clock rate of the main loop prevents LEDs from blinking too fast */
always @ (posedge clk_4800) begin
if (ftdi_rx == 0) ledrx <= ~ledrx;
if (ftdi_tx == 0) ledtx <= ~ledtx;
end
endmodule
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