corrected verilog to pass linter (mostly) and changed 8 bit counter to 4 bit counter (to utilize overflow).

	modified:   Makefile
	modified:   pins.pcf
	modified:   top.v
	renamed:    uart_trx.v -> uart_tx_8n1.v

4 files changed, 28 insertions, 21 deletions

diff --git a/Makefile b/Makefile
index 25ae12b..9225859 100644
--- a/Makefile
+++ b/Makefile
@@ -3,19 +3,29 @@ DEVICE = hx1k
 PKG = tq144
 PCF = pins.pcf
 
-FILES = top.v uart_trx.v
+FILES = top.v uart_tx_8n1.v
 
 .PHONY: all clean burn
 
 all: $(PROJ).bin
 
-$(PROJ).bin: $(FILES) Makefile
+%.json: $(FILES)
+	# Lint to catch typos
+#	verilator --lint-only -Wall $(FILES)
 	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -json $(PROJ).json" $(FILES)
+	yosys -ql yosys.log -p "synth_ice40  -top top -json $(PROJ).json" $(FILES)
+
+%.asc: %.json
 	# Place and route using nextpnr
-	nextpnr-ice40 --$(DEVICE) --package $(PKG) --pcf $(PCF) --json $(PROJ).json --asc $(PROJ).asc
+	nextpnr-ice40 --$(DEVICE) --package $(PKG) --pcf $(PCF) --json $< --asc $@
+
+%.rpt: %.asc
+	# Timing
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%.bin: %.asc
 	# Convert to bitstream using IcePack
-	icepack $(PROJ).asc $(PROJ).bin
+	icepack $< $@
 
 burn:   $(PROJ).bin
 	iceprog $<
diff --git a/pins.pcf b/pins.pcf
index e3b914e..b62499b 100644
--- a/pins.pcf
+++ b/pins.pcf
@@ -6,4 +6,4 @@ set_io LED5 95
 set_io hwclk 21
 # FTDI pins for UART
 set_io ftdi_tx 8
-set_io ftdi_rx 9
+#set_io ftdi_rx 9
diff --git a/top.v b/top.v
index 47be0b1..2900acc 100644
--- a/top.v
+++ b/top.v
@@ -15,7 +15,7 @@ module top(input hwclk, output LED1, output LED2, output LED3, output LED4, outp
 	reg [31:0] cntr_1 = 32'b0;
 	parameter period_1 = 6000000;
 
-	/* Byte to send over UART */
+	/* Buffer for byte to send over UART */
 	reg [7:0] uart_txbyte = "I";
 	/* Send data rather than idle */
 	reg uart_send = 1'b1;
@@ -23,8 +23,8 @@ module top(input hwclk, output LED1, output LED2, output LED3, output LED4, outp
 	wire uart_txed;
 
 	/* UART transmitter module - 8 bits, no parity, 1 stop bit
-				9600 baud	byte to be transmitted	send on baud clock	input: tx completed	output: UART tx pin */
-	uart_tx_8n1 transmitter(.clk(clk_9600), .txbyte(uart_txbyte), .senddata(uart_send), .txdone(uart_txed), .tx(ftdi_tx));
+				9600 baud	byte to be transmitted	send on baud clock	output: tx completed	output: UART tx pin */
+	uart_tx_8n1 transmitter(.clk(clk_9600), .txbyte(uart_txbyte), .senddata(uart_send), .txcomplete(uart_txed), .tx(ftdi_tx));
 
 	/* LED register */
 	reg ledval = 0;
@@ -55,21 +55,17 @@ module top(input hwclk, output LED1, output LED2, output LED3, output LED4, outp
 	/* Blink all LED's at ~1s interval */
 	always @ (posedge clk_1) ledval <= ~ledval;
 
-	/* As the first char ("I") is already declared and will be transmitted, count is default 1 */
-	reg [7:0] count = 8'd1;
+	/* 4 bits - counts 0-15. As the first char ("I") is already declared and will be transmitted, count is default 1 */
+	reg [3:0] count = 4'd1;
 
 	always @ (posedge clk_9600) begin
 		/* Set the byte to transmit after last byte has been transmitted */
 		if (uart_txed == 1) begin
-			/* If there are no more bytes of the string to transmit, reset the counter */
-			if (count == 16) count = 0;
-
-			/* Holy message needs to be in little endian order (there should be a macro to do this for us) - bitshift selects 1 character at a time */
-			uart_txbyte = "\n\rootneG llatsnI" >> count*8;
-			count = count + 1;
+			/* Holy message needs to be in little endian order - bitshift selects 1 character at a time */
+			uart_txbyte <= "\n\rootneG llatsnI" >> count*8;
+			//uart_txbyte <= 8'("\n\rootneG llatsnI" >> count*8); //Fully correct, but static casting needs systemverilog support - implicit casting still works fine
+			count <= count + 1;
 		end
 	end
 
 endmodule
-
-
diff --git a/uart_trx.v b/uart_tx_8n1.v
index fe8d67f..f893dab 100644
--- a/uart_trx.v
+++ b/uart_tx_8n1.v
@@ -1,5 +1,5 @@
 /* 8n1 UART module - transmit only */
-module uart_tx_8n1(input clk, input[7:0] txbyte, input senddata, output txdone, output tx);
+module uart_tx_8n1(input clk, input[7:0] txbyte, input senddata, output txcomplete, output tx);
 	/* Parameters */
 	parameter STATE_IDLE = 8'd0;
 	parameter STATE_STARTTX = 8'd1;
@@ -15,6 +15,7 @@ module uart_tx_8n1(input clk, input[7:0] txbyte, input senddata, output txdone,
 
 	/* Wiring */
 	assign tx = txbit;
+	assign txcomplete = txdone;
 
 	/* Transmit on clock */
 	always @ (posedge clk) begin
@@ -39,7 +40,7 @@ module uart_tx_8n1(input clk, input[7:0] txbyte, input senddata, output txdone,
 		if (state == STATE_TXING && bits_sent < 8'd8) begin
 			txbit <= buf_tx[0];
 			buf_tx <= buf_tx >> 1;
-			bits_sent = bits_sent + 1;
+			bits_sent <= bits_sent + 1;
 		end
 			else if (state == STATE_TXING) begin
 				/* Send stop bit (high) */